Feb 11, 2014  Each SPI device responds to its own set of instructions (e.g., a flash device will have a read or erase instruction) and the timing diagram is the link between the conceptual behavior of the instruction and the actual hardware protocol to.

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Custom Solutions – Automatically Generated XJFlash allows you to automatically generate customised programming solutions for the flash devices connected to FPGAs on your board. The functional capabilities of the FPGA are harnessed to provide the fastest possible programming speeds.

XJFlash automatically generates a custom design for each FPGA/flash combination, allowing you to achieve the best programming times, whilst not requiring you to do any FPGA development.* Whether you are using SPI, QSPI or parallel NOR flash connected to an FPGA from Altera, Xilinx, Microsemi or Lattice – XJFlash will provide you with a programming solution optimised for your board. *A licensed version of the relevant FPGA manufacturer’s tools will be required during the configuration of XJFlash. Free versions are sufficient for many devices. Test Integration XJFlash is fully compatible with the rest of the XJTAG development system. All XJFlash programming can be run as part of an boundary scan test project. Configurable Flash Programming It doesn’t matter whether you need to program a single flash device, or multiple devices that are connected in series, to expand the address space, or in parallel, to make a wider data bus, you can use XJFlash to speed up your programming operations. Custom development XJFlash can also be used for standalone programming requirements including direct access to I²C and SPI busses or custom protocols such as Microchips ICSP.

The required connections do not need to come from an FPGA on the target board. Providing the protocol signals are available on a header on that board, it should be possible to use XJFlash to achieve fast programming as part of an XJTAG solution. Erase – The flash can be erased using one of two algorithms.

The basic erase will simply erase all blocks within a defined range (this may be the whole flash or just the space needed for the image to be programmed). The more intelligent erase will use the fact that it is quicker to read the flash than to erase it; as such it reads from each address and only starts erasing if some data is found. This step can be skipped if it is known that the flash will always be blank before it is programmed. Example time – intelligent erase enabled: 0.9 s with a device already erased, to 23 s with a fully programmed device (limited by erase time of device). Can I use XJFlash? In order to use XJFlash all of the data, address and control signals on the flash device(s) must be connected to an FPGA on the target board. This can be a configuration PROM, or a flash device connected to any general purpose I/O pin.

These connections can be direct, indirect, dedicated or shared: Direct connections – YES The flash is directly connected to the FPGA. Indirect connections – YES • The flash is connected to the FPGA via a buffer • Some of the address signals are shared with the data signals and connected via a latch.